FIG. 5 is a block diagram showing a transmission output control apparatus having a conventional type of amplifying device.
In FIG. 5, the reference numeral 1 indicates an input terminal to which a transmitter signal to the transmission output control apparatus is inputted, and the reference numeral 2 indicates an amplifier circuit in an exciting stage for amplifying the signal inputted into this input terminal 1. The reference numeral 3 is an amplifier circuit in a final stage for receiving a signal outputted from the amplifier circuit 2 in the exciting stage and amplifying power of the signal, said amplifier circuit comprising a FET (field effect transistor). The reference numeral 4 is an output terminal for taking out transmission output with the power amplified in an amplifier circuit 3 in the final stage.
The reference numeral 5 indicates a power supply terminal for supplying a drain voltage to the FET in the amplifier circuit 3 in the final stage, and the reference numeral 6 indicates a drain voltage switching means for switching a drain voltage supplied from the power supply terminal 5 to the FET in the amplifier circuit 3 in the final stage.
The reference numeral 7 is a coupler for taking out output from the amplifier circuit 3 in the final stage branching a portion thereof, and the reference numeral 8 indicates a detector circuit for detecting a signal taken out in the coupler 7 and outputting a signal corresponding to an output power from the amplifier circuit 3 in the final stage. The reference numeral 9 is a control means for generating a signal for specifying output power from the amplifier circuit 3 in the final stage, and this control means also controls the drain voltage switching means 6.
The reference numeral 10 is a power control circuit for generating a control signal for controlling output from the amplifier circuit 2 in the exciting stage according to a signal outputted from the detector circuit 8 as well as to the output power select signal generated in the control means 9. The reference numeral 11 is a power control transistor for controlling output from the amplifier circuit 2 in the exciting stage according to a control signal from the power control circuit 10.
Next description is made of the operation of the circuit.
At first, a control signal for controlling the drain voltage switching means 6 is outputted from the control means 9. When this control signal is at a low level, a switching transistor in the drain voltage switching means 6 is energized. In this case, the drain voltage from the power supply terminal 5 is supplied to a drain terminal of the FET in the amplifier circuit 3 in the final stage. With this, operation of the amplifier circuit 3 in the final stage is started, and power of an input signal from the input terminal 1 amplified in the amplifier circuit 2 in the exciting stage is amplified with the signal outputted from the outputted terminal 4 through the coupler 7.
On the other hand, a portion of the output from the amplifier circuit 3 in the final stage is branched by the coupler 7 and is inputted into the detector circuit 8. The detector circuit 8 detects a portion of the output from the amplifier circuit 3 in the final stage branched by the coupler 7 and generates a signal corresponding to output power from the amplifier circuit 3 in the final stage. The power control circuit 10 compares an output power select signal generated by the control means 9 to the signal corresponding to output power from the amplifier circuit 3 in the final stage which is generated in the detector circuit 8, generates a control signal so that the output power from the amplifier circuit 3 in the final stage is equalized to the power selected according to the output power select signal generated in the control means 9, and sends the signal to the power control transistor 11.
The power control transistor 11 controls a voltage loaded to the amplifier circuit 2 in the exciting stage according to a control signal generated in the power control circuit 10 and provides controls so that the output power from the amplifier circuit in the final stage is equalized to and maintained at the same level as the power selected according to the output power select signal generated in the control means 9.
Configuration of an amplifier apparatus based on the conventional technology is as described above, so that a voltage is always loaded to a drain terminal of the FET in the amplifier circuit 3 in the final stage. Generally, in a case where a drain voltage is loaded to an amplifying means such as an FET or an NPN transistor, isolation between the gate and drain becomes poorer, and sometimes power inputted to the gate terminal may be leaked to the drain terminal. For this reason, in a case where low output power is required such as when it is required that output power from an amplifying device is smaller than input power thereto, even if a voltage loaded to the amplifier 2 in the exciting stage is controlled, the power inputted into the gate terminal is leaked to the drain terminal and is added to the output power therefrom because of the characteristics of the amplifying means as described above. For this reason, even if lower output power is required, sometimes it may be impossible to suppress the output power to a certain level or below.